The present invention relates generally to semiconductor devices and methods of production thereof, and more particularly to semiconductor devices having contact holes and methods of production thereof.
Semiconductor integrated circuits continue to become more highly integrated. As integration increases, the size of integrated circuit elements, for example transistors, can become increasingly small. As elements become smaller, the spacing between adjacent elements, such as conductive lines or xe2x80x9cwires,xe2x80x9d can become smaller too. Smaller spacing constraints can result in decreased spacing margins for a contact hole that is to be formed between and/or adjacent to wires. This will be explained with reference to FIGS. 12 and 13.
FIGS. 12 and 13 illustrate spacing margins for two examples of a contact hole 1200. The contact hole 1200 is formed in two interlayer insulating films, shown as 1202 and 1204, and can expose a diffusion layer 1206. Wires, shown as 1208, are formed between the interlayer insulating layers (1202 and 1204), and a contact hole 1200 is formed between the wires 1208.
It is noted that FIG. 12 illustrates a contact hole 1200 having a smaller diameter than the contact 1200 of FIG. 13.
Typically, the formation of a contact hole 1200 can include certain minimum requirements. First, the diffusion layer 1206 should be sufficiently exposed to allow contact with the diffusion layer 1206. Second, wires 1208 should be sufficiently isolated from an electroconductive layer (not shown) that is to be deposited into the contact hole 1200. Ideally, such requirements meet particular absolute values. In reality, however, due to process and other variations, a certain amount of variation is typically accounted for in order to meet such requirements in a practical sense.
FIGS. 12 and 13 include particular measurements. Measurement xe2x80x9ca1xe2x80x9d represents the exposed area of diffusion layer 1206. Measurement xe2x80x9cb1xe2x80x9d represents the distance between the wall of the contact hole 1200 and a wire 1208. It is desirable to have a large xe2x80x9ca1xe2x80x9d value, because a larger exposed area of a diffusion layer can lead to lower contact resistance. One skilled in the art would recognize that lower contact resistance can lead to faster and/or lower power semiconductor devices. Of course, if the value a1 was zero, it would fail the requirements described above. Typically, a value a1 must meet a minimum value, or have a certain margin to account for variations in the size of features introduced by the fabrication process.
It is also desirable to have a large xe2x80x9cb1xe2x80x9d value. The larger the value of xe2x80x9cb1,xe2x80x9d the larger the distance between the internal wall of contact 1200 and wire 1208. A larger such distance xe2x80x9cb1xe2x80x9d can result in reduced risk of a short-circuit condition (short) between an electroconductive layer formed in the contact hole 1200 (not shown) and a wire 1208. A shorter such distance xe2x80x9cb1xe2x80x9d can result in an increased risk of a short between an electroconductive layer (not shown) and a wire 1208. Such an increased risk is not desirable. Of course, if b1 was zero, it would fail the requirements described above. As in the case of the value a1, the value b1 must typically meet a minimum value, or have a certain margin to account for variations in the size of features introduced by variations in the fabrication process.
Meeting the various requirements of a contact can be complicated because, as shown in FIGS. 12 and 13, the values a1 and b1 have a xe2x80x9ctrade-offxe2x80x9d relationship with respect to one another. In particular, if the value b1 (i.e., the distance between the internal wall of contact hole 1200 and a wire 1208) is made larger, the resulting a1 value (i.e., the exposed area of diffusion layer 1206) can be smaller. This relationship is shown in FIG. 12. Conversely, if the value a1 (i.e., the exposed area of diffusion layer 1206) is made larger, the resulting value b1 (i.e., the distance between the internal wall of contact hole 1200 and a wire 1208) can be smaller. This relationship is shown in FIG. 13.
FIGS. 14 and 15 show profiles of a semiconductor device after an electroconductive layer 1210 is deposited into a contact hole 1200. FIGS. 14 and 15 can be considered to correspond to FIGS. 12 and 13, respectively.
A number of countermeasures have been proposed to further prevent a short between an electroconductive layer deposited in a contact hole and an adjacent wire. Such countermeasures include a side-wall contact structure or tapered contact structure. The examples of FIGS. 12-15 set forth examples of a side-wall contact structure and a tapered contact structure. Accordingly, a side-wall contact structure and a tapered contact structure will now be described with reference to FIGS. 12-15.
A side-wall contact structure includes a side-wall insulating film formed on the internal wall of a contact hole 1200, and is shown in FIGS. 12-15 as item 1212. In such a structure, if a contact hole 1200 was formed in such a way that it would result in a value b1 of zero (namely, opening the contact hole 1200 would expose a wire 1208) side-wall 1212 could serve to intervene between a wire 1208 and an electroconductive layer 1210 deposited into a contact hole 1200, preventing a short between the two. The side-wall contact structure is shown in Japanese Patent Application Laid-Open No. 10-144788.
In a tapered contact structure, the internal wall of a contact hole 1200 is not vertical, but inclined. Consequently, the closer the contact hole 1200 is to the bottom, the smaller the area of the contact. This is illustrated in FIGS. 12-15, which show contact holes 1200 that are larger toward the top than toward the bottom. Consequently, because the tapered contact has a smaller area as it proceeds deeper toward the bottom of the contact, the distance b1 (between the wall of the hole 1200 and wire 1208) can be larger than the case where a contact hole is essentially cylindrical. This can lead to increased spacing margins and/or increase the resulting boundary between the internal wall of a contact hole and an adjacent wire.
In the conventional cases described above, side-wall contact structures and tapered contact structures can be employed to prevent shorts between an electroconductive layer 1210 and a wire 1208. Unfortunately, both structures tend to reduce the resulting exposed area a1 of the diffusion layer 1206.
In more detail, in the case of the side-wall contact structure, the resulting side-wall 1212 can cover the diffusion layer 1206. In particular, the exposed diffusion layer 1206 is covered by the thickness of side-wall 1212 on all sides.
In the case of the tapered contact structure, the internal wall of a contact hole 1200 has an inclined surface. Obviously, as the internal surface is inclined, the resulting exposed area of diffusion region 1206 becomes smaller.
As can be seen from the above description, while the employment of a side-wall contact structure and/or a tapered contact structure can be effective in reducing shorts between an electroconductive layer 1210 and an adjacent wire 1208, such approaches can also be accompanied by corresponding reductions in the exposed area a1 of the diffusion layer 1206. As noted above, this can lead to undesirable increases in contact resistance.
In light of the above drawbacks in conventional approaches, it would be desirable to arrive at a semiconductor structure, and method of production thereof, that can prevent shorts between an electroconductive layer 1210 and an adjacent wire 1208, while at the same time exposing a larger portion of a diffusion layer.
According to one embodiment of the present invention, a semiconductor device can include an interlayer insulating film formed over a semiconductor substrate that includes a contact hole formed therein. A side-wall film can cover a portion of the internal surface of the contact hole. An electroconductive layer can be formed in the contact hole over the side-wall film. A side-wall insulating film can preferably include a laminated structure that includes two side-wall insulating films, including a first side-wall insulating film and a second side-wall insulating film that can have different etch rates.
According to one aspect of the embodiments, the electroconductive layer can preferably connect a diffusion layer in the substrate and a capacitive electrode formed on the interlayer insulating film. Preferably, a portion of the internal surface of the contact hole can face the electroconductive layer while another portion can face the diffusion layer.
According to another aspect of the embodiments, the interlayer insulative film can preferably have a laminated structure that includes a first interlayer insulative film and a second interlayer insulative film. A wire layer can be formed between the first interlayer insulative film and the second interlayer insulative film.
According to another embodiment of the invention, a semiconductor device includes a substrate having a diffusion layer formed therein, an interlayer insulative film formed over the substrate, a contact hole formed through the interlayer insulative film to expose at least a portion of the diffusion layer. A first side-wall insulating film can cover the internal surface of the contact wall, and not completely cover the interlayer insulating film. A second side-wall insulating film can cover the first side-wall insulating film. An electroconductive layer can fill the contact hole. Preferably, the first and second side-wall films can have different etch rates when subjected to a particular etch. Preferably, the interlayer insulating film can have a laminated structure having first and second side-wall insulating films. A wire layer can be formed between the interface of the first and second side-wall insulating films.
According to one embodiment, a method of manufacturing a semiconductor device can include forming a diffusion layer in a semiconductor substrate, forming an interlayer insulating film on the substrate, forming a contact hole through the interlayer insulating film and exposing the diffusion layer, forming a first side-wall insulating film that covers the internal surface of the contact hole and the exposed diffusion layer, forming a second side-wall insulating film that covers the first side-wall insulating film. The method may further include removing at least a portion of the second side-wall insulating film that covers the diffusion layer thereby exposing a portion of the first side-wall insulating film. A portion of the first side-wall insulating film over the diffusion layer can be removed with a wet etch.
According to one aspect of the embodiment, removing at least a portion of the second side-wall insulating film includes exposing a lateral surface of the first side-wall insulating film and exposing the diffusion layer by removing portions of the first and second side-wall insulating layers over the diffusion layer.
According to one aspect of the embodiment, removing at least a portion of the second side-wall insulating film includes exposing the top surface of the first side-wall insulating film without substantially removing the portion of the first side-wall insulating layer that covers the diffusion layer.